There is no requirement on voltage levels or data rates, and many SPI implementations can use clock rates greater than 10 MHz. Figure 1 shows a block and timing diagram of the 34950A bank 1, when ...

Configurable for all 4 SPI modes* this block acts as a single slave. The design targets the 0.18um CMOS (ca18ha) process offered by Jazz. The MR74040 consists of 32, 16-bit wide R/W registers, 28 of ...