The block diagram of the Transmitter architecture is given in Figure 2. The input to the transmitter is 64-bit data at 155.50 MHz rate. The output on SPI 4.2 bus is 311 MHz DDR 16-bit data. Hence the ...

Figure 1. System Block Diagram showing SPI-S The SPI-S effort was jointly started by the Network Processor Forum (NPF) and OIF in summer 2004. Since then, NPF and OIF have merged and the OIF Physical ...