A high-speed DDR2, DDR2/3, or DDR3 ... interface between the system-on-chip (SoC) and off-chip memory requires specialty circuits. These circuits, often referred to as a physical layer (PHY), comprise ...

This fully-integrated macro cell architecture provides the physical layer (PHY) interface between the controller logic and DDR3 DRAM devices to achieve data rates up to 1.6Gbps. "Rambus' ...

Intelli(TM) DDR3 Delivers High-Performance System Aware IP(TM) Memory Interface Solution FREMONT, Calif. -- Jul 14, 2008 -- Virage Logic Corporation (NASDAQ:VIRL), the semiconductor industry's trusted ...

Optimized for low power and reduced silicon area, the Rambus DDR3 memory controller interface cell is designed to accommodate a broad range of applications including PC main memory, consumer ...

ADATA’s XPG Gaming v.2.0 series DDR3 memory has a new top dog with the introduction ... To further ensure reliability, a screw-lock mechanism improves cooling efficiency for long-term use.