Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several ...

The step down from 100 mV to 2 mV can be performed with only two /spl mu/pots. New millivolt-amplifiers with gain factors of 11, 50, and 121 in conjunction with PMJTCs are developed to measure the ...