System Verilog Macro: A Powerful Feature for Design Verification …
SV macro is one of the most powerful features out there and if used properly with a thorough understanding and applied wisely in a DV project, it can help to save a lot of time and can make the code more readable and efficient. This paper shows how, using SV macro with the proper syntaxes, a DV engineer can break up the larger complex code in smaller chunk and can reuse it at many places.
Enhancing VLSI Design Efficiency: Tackling ... - Design And Reuse
The objective of this paper is to illustrate congestion, shorts, and practical approaches to fix both issues at lower/higher technology nodes. This paper also includes PnR tool (ICC2) related commands and their uses to overcome the mentioned issues.
Understanding Logic Equivalence Check (LEC) Flow and Its …
Logic Equivalence Check, popularly known as LEC is one of the most important parts of the ASIC VLSI design. Formal verification techniques have been developed using mathematical proof rather than simulation or test vectors to provide a higher level of verification confidence on properties. For example, the implementation can be either a Verilog ...
Design Rule Checks (DRC) - A Practical View for 28nm Technology
This whole process is called Design Rule Checking (DRC). There are many design rules at different technology nodes, a few of which are mentioned below. Types of DRCs: Minimum width and spacing for metal. Minimum width and spacing for via. Fat wire Via keep out Enclosure. End of Line spacing. Minimum area.
UVM RAL Model: Usage and Application - Design And Reuse
UVM RAL is an object-oriented model for registers inside the design. To access these design registers, UVM RAL provides ready-made base classes and APIs. Some of the RAL model features are: Just like design, it supports different register attributes like R/W, RO, WO, W1C, etc. Supports two different paths for register access, frontdoor and ...
A Guide on Logical Equivalence Checking - Design And Reuse
A Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits. By Pratik Patel, Prathmesh Oza and Rakesh Parmar (eInfochips) Introduction. The VLSI design cycle is divided into two phases: Front-end and Back-end. Front-end covers the architectural specifications, coding and verification, whereas back-end involves the physical ...
Demystifying MIPI C-PHY / DPHY Subsystem - Design And Reuse
For D-PHY this can be accomplished by using four-lane D-PHY, using 10 wires, each Lane running at 1.0Gbps/lane. To obtain the same aggregate data rate at the same or lower transition rate with C-PHY, we can use two-lanes C-PHY, with 6 wires, running at 0.875Gsps, which is less than the 1.0Gsps for the D-PHY.
System Verilog Assertions Simplified - Design And Reuse
System Verilog Assertions Simplified. By Smit Patel, eInfochips. Abstract. Assertion is a very powerful feature of System Verilog HVL (Hardware Verification Language). Nowadays it is widely adopted and used in most of the design verification projects. This article explains the concurrent assertions syntaxes, simple examples of their usage and ...
A Guide on Logical Equivalence Checking - Flow, Challenges, and …
A Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits. The VLSI design cycle is divided into two phases: Front-end and Back-end. Front-end covers the architectural specifications, coding and verification, whereas back-end involves the physical implementation of the design on the targeted technology node.
UPF Constraint coding for SoC - A Case Study - Design And Reuse
Table 1 Power State Tables for SoC. Power switch is created for every switchable power domains. Bottom-Up Approach: A separate UPF constraint file can be created for each subsystem and all the subsystem UPF files are loaded in the SoC Top UPF file using load_upf command with set_scope specifying the corresponding instance name. In Bottom-UP approach each subsystem RTL plus its corresponding ...